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NXP Semiconductors /LPC13xx /USB /DEVINTCTRL

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Interpret as DEVINTCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FRAME_CLR)FRAME_CLR 0 (EP0_CLR)EP0_CLR 0 (EP1_CLR)EP1_CLR 0 (EP2_CLR)EP2_CLR 0 (EP3_CLR)EP3_CLR 0 (EP4_CLR)EP4_CLR 0 (EP5_CLR)EP5_CLR 0 (EP6_CLR)EP6_CLR 0 (EP7_CLR)EP7_CLR 0 (DEV_STAT_CLR)DEV_STAT_CLR 0 (CC_EMPTY_CLR)CC_EMPTY_CLR 0 (CD_FULL_CLR)CD_FULL_CLR 0 (RXENDPKT_CLR)RXENDPKT_CLR 0 (TXENDPKT_CLR)TXENDPKT_CLR 0RESERVED

Description

USB Device Interrupt Clear

Fields

FRAME_CLR

Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP0_CLR

USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP1_CLR

USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP2_CLR

USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP3_CLR

USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP4_CLR

USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP5_CLR

USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP6_CLR

USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
EP7_CLR

USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
DEV_STAT_CLR

Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
CC_EMPTY_CLR

The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
CD_FULL_CLR

Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
RXENDPKT_CLR

The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
TXENDPKT_CLR

The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data